? semiconductor components industries, llc, 2015 september, 2015 ? rev. 3 1 publication order number: ncp392c/d ncp392c adjustable front end overvoltage protection controller with protected vbus output the ncp392c is an overvoltage front end protection controller and is able to disconnect the systems from its output pin in case wrong input operating conditions are detected, up to +28 v. thanks to this device using internal nmos, no external device is necessary, reducing the system cost and the pcb area of the application board. internal ovlo threshold is available, or can be adjusted if an external resistor bridge is used. at power up (en pin = low level), the vout turns on tstart time after internal timer elapsed. the ncp392c features an acok pin that indicates faulty condition. features ? over?voltage protection up to + 28 v ? on?chip low r ds(on) nmos transistors: typical 34 m ? over?voltage lockout (ovlo) ? externally adjustable ovlo ? internal 15 ms startup delay ? shutdown en input ? acok status pin ? + 100 v surge capability , in compliance with iec61000?4?5 standard ? compliance to iec61000?4?2 (level 4) standard 8 kv (contact) 15 kv (air) ? esd ratings: machine model = b (200 v) human body model = 2 (2 kv) ? csp?12 package 1.3 x 2.0 mm, 0.4 mm pitch ? this is a pb?free device typical applications ? cell phones ? tablets ? camera phones ? digital still cameras ? personal digital applications wlcsp 12 fcc suffix case 567jm pin connection www. onsemi.com marking diagram ordering information see detailed ordering, marking and shipping information on page 9 of this data sheet. 392cx = specific device number 392cx = (x = r or s) a = assembly location y = year ww = work week = pb?free package 392cx ayww en out out pgnd out in pgnd ovlo in in pgnd a b c 123 4 (top view) acok
ncp392c www. onsemi.com 2 figure 1. typical application circuit ncp392c b4 a4 c4 gnd output a2 a3 b2 b3 c2 c3 c1 b1 a1 charger pmic /flag /en 0.1 f in in in ovlo gnd gnd en / acok out out out b+ functional block diagram figure 2. functional block diagram ovlo tsd charge pump input vref gate driver control logic and timer sel ovlo ovlo gnd internal ovlo selected external ovlo r1 r2 fault & en c1 c2 selected acok en en
ncp392c www. onsemi.com 3 pin function description en out out pgnd acok out in pgnd ovlo in in pgnd a b c 123 4 (top view) figure 3. pinout table 1. ncp392 pin description pin pin name type description a1 en i/o enable pin bar. the device enters in shutdown mode when this pin is tied to a high level. in this case the output is disconnected from the input. a2, a3, b2 out output output voltage pins. these pins follow in pins, with debounce time, when ?no fault? are detected. the outputs are disconnected from the vin power supply when the input voltage is below uvlo, above ovlo threshold or internal thermal protection is exceeded. the three out pins must be hardwired together and used for power dissipation. a4, b4, c4 pgnd power ground. the three gnd pins must be hardwired together and connect to the system gnd. b1 acok output acok pin: fault indication pin. open drain. this pied in tied low if vin is within uvlo and ovlo range. 1 v in < v uvlo or v in v ovlo 0 voltage stable b3, c2, c3 in power input voltage pins. these pins are connected to the power supply. the three in pins must be hardwired together. c1 ovlo input external ovlo adjustment. connect external resistor bridge to ovlo pin to select a different ovlo threshold. connect ovlo pin to gnd if not used. in this case internal ovlo will be selected.
ncp392c www. onsemi.com 4 table 2. maximum ratings rating symbol value unit minimum voltage (in, ovlo to gnd) vmin in ?0.3 v minimum voltage (all others to gnd) vmin ?0.3 v maximum voltage (in to gnd) vmax in 29 v maximum voltage (ovlo to gnd) vmax ovlo 14 v maximum voltage (out to gnd) vmax out 22 v maximum voltage (all others to gnd) vmax 7 v maximum dc current imax 4.5 a peak input current ipeak 8 a thermal resistance, junction?to?air r ja 70 c/w operating ambient temperature range t a ?40 to +85 c storage temperature range t stg ?65 to +150 c junction operating temperature t j + 125 c esd withstand v oltage (iec 61000?4?2) human body model (hbm), model = 2 (note 1) machine model (mm) model = b (note 2) v esd 15 kv air, 8 kv contact 2000 v 200 v kv v v moisture sensitivity msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. human body model, 100 pf discharged through a 1.5 k resistor following specification jesd22/a114. 2. machine model, 200 pf discharged through all pins following specification jesd22/a115
ncp392c www. onsemi.com 5 table 3. electrical characteristics min / max limits values (?40 c < t a < +85 c) and v in = +5 v (unless otherwise noted). typical values are t a = +25 c. characteristics symbols conditions min typ max unit input voltage range v in , v ovlo 2.8 28 v under voltage lockout uvlo v in rising 2.8 v under voltage lockout hysteresis uvlo hyst v in falling ? 60 ? mv internal over voltage lockout threshold ovlo v in rising (note 3) ovlo pin tied to gnd ? 25 c ncp392cr 13.4 13.8 14.2 v ncp392cs 15 15.5 16 internal over voltage lockout hysteresis ovlo hyst v in falling (note 3) ovlo pin tied to gnd ? 25 c 1.5 2.5 % external ovlo reference ovlo _ext ncp392cr 1.12 1.20 1.24 v ncp392cs 1.18 1.221 1.26 external adjustable ovlo 4 20 v over?voltage lockout hysteresis ovlo exthyst v in falling 2 % external ovlo select threshold ovlo sel 0.2 0.3 v vin versus vout resistance r dson v in = 5 v, en = gnd, ?40 c < t j < 125 c 34 50 m supply quiescent current i dd no load, en = 0.4 v 58 100 a standby current i stb no load, en = 1.2 v, 6 a ovlo supply current i in_ovlo v ovlo = 3 v, v in = 5 v, v out = 0 v 60 100 a ovlo select leakage i ovlo 100 na logic en voltage high v ih 1.2 v en voltage low v il 0.4 v acok output low voltage v ol i sink = 1 ma 0.4 v timings start up time t start from v in > 2.8 v to 10% v out, en low 15 ms enable time t en v in present, from en high to low, 10% v out 15 ms soft start t rise from 10% to 90% of v out , c load 100 f, rload, 100 , en low 1 ms acok start up time t start2 from vin valid to acok tied low, en low or high 30 ms turn off time t off surge off time 100 ns disable time t dis from en >1.2 v to 90% v out. no load 20 s ovlo turn off time t ovlo v in rising 2 v/ s 1.5 s tsd thermal shutdown tsd 140 c thermal shutdown rearming tsd rearm 115 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. please contact your on semiconductor representative for additional ovlo threshold. electrical parameters are guaranteed by correlation across the full range of temperature.
ncp392c www. onsemi.com 6 operation the ncp392c provides over?voltage protection for positive voltage surge, up to + 28 v. an additional clamp, between in and gnd, protects the part against surge test, in compliance with iec 61000?4?5 standard. a acok open drain fault indicator is provided. this signal indicates whether input voltage is within the valid range. under?voltage lockout (uvlo) to ensure proper operation under any conditions, the device has a built?in under?voltage lock out (uvlo) circuit. this circuit has a built?in hysteresis to provide noise immunity to transient conditions. over?voltage lockout (ovlo) to protect connected systems on vout pin from over?voltage, the device has a built?in over?voltage lock out (ovlo) circuit. during over?voltage condition, the output remains disabled until the input voltage is above ovlo ? hysteresis. figure 4. uvlo, ovlo and en functionality /en vin ovlo vout uvlo t vbus t start t rise t off t start t rise t off t soft t soft
ncp392c www. onsemi.com 7 figure 5. external connection to gnd of ovlo input vref sel ovlo gnd internal ovlo selected fault & en acok if ovlo pin is not grounded, and by adding external bridge resistor on ovlo pin, between in and gnd, overvoltage protection can be adjusted as following: figure 6. external connection to resistor bridge of ovlo input vref sel ovlo gnd internal ovlo selected external ovlo r1 r2 fault & en c1 c2 acok selected new_ovlo th ovlo ext r 1 r 2 r 2 (eq. 1) with: ovlo ext = 1.221 v typical (ovlo external reference) example: new_ovlo th target 12 v. r1 r2 ovlo 1.221 1 r2 12 1.221 1 8.828 r2 (eq. 2) taking into account external input bridge doesn?t have excessive current consumption, and 1% is recommended: r2 arbitrarilly fixed at 1.05 m . r1 = 9.269 m (9.31 m standard value) obtained typical ovlo = 12.04 v c 1 and c 2 should be selected in such a way that the time constant r 1 c 1 = r 2 c 2 . en input to enable normal operation, the en pin has to be at low level. there is neither internal pull up, nor internal pull down connected to en pin. if not externally driven, this pin and so ncp392c switch are undefined state. a high level on the pin, disconnects out pin from in pin. table 4. control logic modes ovp state ncp392cx ovlo ext low high en low on t start 15 ms off high off off
ncp392c www. onsemi.com 8 vin ovlo vout uvlo high?z figure 7. en and acok associated timers t start t start2 t rise t off acok en t start t rise t start2 acok pin the ncp392c version integrates a acok status indicator. this is a drain pin tied low when no fault is present (no tsd, no under voltage, no over voltage). when disabled, the acok feature is disabled too and the output pin is in high impedance mode. thermal shutdown protection in case of internal overheating, the integrated thermal shutdown (tsd) protection allows to open the internal mosfet in order to instantaneously decrease the device temperature. embedded hysteresis allows to reengage the mosfet when the junction temperature decreases. if the fault event is still present, the temperature increases again and engages the thermal shutdown one more time until fault event disappeared. pcb recommendations to limit internal power dissipation, pcb routing must be carefully done to improve current capability. the ncp392c is declined in a csp package. so power dissipation can be decreased on each pin connection but main thermal area must be as lar ge as possible around in and out pins. t aking into account and respectively, four in and out pins must be hardwired together on the pcb. maximum power dissipation can be calculated with the following formula: t j t a r ja p d (eq. 3) t j : junction temperature t a : ambient temperature r ja : thermal resistance of the junction to air through the case and board. p d : power dissipation = r ds(on) x i 2 esd tests the ncp392c fully supports the iec61000?4?2, level 4 (input pin, 1 f mounted on board). that means, in air condition, v in has a 15 kv esd protected input. in contact condition, v in has 8 kv esd protected input. please refer to figure 8 to see the iec 61000?4?2 electrostatic discharge waveform.
ncp392c www. onsemi.com 9 figure 8. i peak = f(t) / iec61000?4?2 usb otg support when used in an application that has to supply voltage to an external accessory (i.e. usb otg), the part is able to supply 1.8 a to the accessory. if v in = 0 v when +5.0 v otg is applied to the out pin, current will flow through the mosfet body diode and, as soon as the output voltage will be higher than the v uvlo voltage (2.8 v) plus body diode forward voltage, the part will turn fully on and current will be supplied to the accessory with minimum drop. in that case, the acok pin will keep high?z state. ordering information device marking option package shipping ? ncp392crfcct1g 392cr ovlo 13.8 v wlcsp (pb?free) 3000 / tape & reel NCP392CSFCCT1G 392cs ovlo 15.5 v ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp392c www. onsemi.com 10 package dimensions wlcsp12, 1.3x2.0 case 567jm issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 a3 0.04 ref b 0.24 0.30 e 0.40 bsc 0.60 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.08 c 12x b 4 c b a 0.10 c a1 a2 c 0.17 0.23 0.25 12x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e a2 0.36 ref recommended package outline 123 pitch pitch a1 e 2.01 2.04 a e/2 detail a a3 detail a die coat (optional) d 1.26 1.31 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp392c/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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